1. Field of the Invention
The present invention relates to a system for detecting and diagnosing problems due to excessive levels of current switching noise and more particularly to noise generated by pre-identified contributors of switching noise.
2. Description of the Prior Art
Computers can be used to assist in the design, development and production of complex systems. The technological evolution of electronic computer systems over the past thirty years has been made possible by the use of computers themselves to assist in designing new generations of computers.
The dramatic rate of change in the circuits and packages used as building blocks by digital circuit designers has been the predominant influence on the evolution of computer systems. Design complexity has also grown with the increase in the number of package levels which product designers personalize. In early technology, the circuit cards consisted primarily of a predesigned set. The specification of the panel and cable wiring was the essential physical design variable. Later the cards became more unique and design of the circuit cards became an additional physical package design variable. LSI brought with it the requirement for designing chips.
While the initial approach to assisting engineers in reaching accuracy goals was to compare the detailed design with sets of predefined rules, attention has recently been given to helping with the analysis of a design's functionality. This process is called design verification. Design verification denotes a host of tasks performed by a logic design engineer in order to ascertain the correctness of his design. There are several reasons for the engineer to verify his design. The initial specification of the design is basically behavioral, is often expressed informally in prose and contains inherent ambiguities. Designers require a procedure to ensure that their design is a correct implementation of the specification.
Also, the complexity of the design forces designers to think in terms of multiple conceptual levels. In particular, the detailed implementation of some portions of the design may affect the general design of other portions. Thus, implementation constraints and the interactions between portions of the design often prevent a pure "top-down" design process. The designer needs tools capable of verifying the correctness of a mixed model of the design (e.g., with regard to logic function, delays, timing, etc.), with each portion described on an appropriate conceptual level. Design iterations are commonplace, as conflicting partial solutions are resolved. Again, verification tools are needed to check self-consistency of the total design.
Lastly, human errors and oversights are unavoidable because of the size and complexity of the designs being considered. Thus, tools are needed to check for such problems whenever manual intervention occurs during the design process.
Without computer simulation systems, engineers are forced to build physical hardware prototypes to validate their designs. Early LSI technology users often constructed a prototype in a pre-LSI technology. A need was developed for logic simulation tools to aid in design verification and to alleviate the need for hardware modeling. Due to the difficulty of prototyping dense LSI technologies, simulation and modeling has become a widely accepted practice.
In computer simulation systems, the primary data base is organized for random access processing. All types of design data (logical, physical, control and the like) can be stored for all levels of packaging. This structure avoids many of the problems inherent with serial access systems.
Moreover, the data structure is parameterized so that it can be adapted to varying packaging nomenclatures and requirements. This allows the system to accommodate designs which include many varieties of chips, modules, cards, planars and boards.
Methods of segmenting the data base have been developed to accomplish hierarchical processing. This allows the chips to be designed independently of, but in parallel with, the module or card. When the chip design is complete, the necessary data is available for completing the processing of the next level of package. Since the necessary data is a small subset of the entire chip design data, very dense second- and third-level packages can be processed. Test pattern generation and design verification capabilities are generally provided.
Programs have been implemented to audit the design process. This allows the system to ensure that the right level of technology rules is used, that the design, checking and test-generation programs all run successfully, that no severe design errors are detected and, most importantly, that if the design data were changed during the process, the necessary programs are rerun to ensure total design data integrity prior to manufacturing. This feature has promoted a design discipline which has made masterslice (gate array) chip design very reliable.
Simulation has been used for functional design verification in the recent past. The simulator can be a nominal delay simulator, utilizing the concept of significant event simulation. The significant event technique is important since it limits the amount of examination and calculations done by the simulator. By considering only those design elements which could possibly change logical state as a result of the latest change of state, running time is minimized. Settling due to oscillations is solved by introducing artificial delays sufficiently long for small spikes to disappear.
A significant development has been three-valued simulation. Three-valued algebra helps logic simulators detect and handle logic circuit hazard and race conditions. A third value, "X," is added to the stable Boolean values "0" and "1" to allow analysis of networks in which some signals are not in stable states.
It would be advantageous to use four-value modeling to allow more accurate results than those obtained by three-value simulation. In addition to "0," "1," and "X," a "U" value would be added, denoting an uninitialized value. At the start of simulation, all nets would be assigned the value U. In the course of simulation, Us would be replaced by other values. If any remain at the conclusion of the simulation, however, it would mean that specific nets were not affected by the stimulus applied, indicating either a design error or incomplete coverage by that stimulus.
It would also be advantageous to introduce varying degrees of delay and timing accuracies, namely, zero delay, unit delay, nominal delay and extreme delay. Any combination of value range and delay type appropriate to a phase of product development would be able to be chosen.
Space-efficient host packages have been developed for VLSI logic chips. The multichip module is such a package, increasingly used in modern high-performance data processing equipment.
Although multichip module packaging solves many design problems, it introduces or intensifies certain other design and manufacturing problems. Among the design problem categories affected is electrical noise. Among the several types of noise which can present design problems is switching or "Delta I" noise. This noise is generated by high current switchings in the undecoupled inductances of chip and module power and signal distribution networks. It is caused primarily by the switchings of interchip and intermodule drivers and by transmission line terminators used in high-speed interchip and intermodule signal nets. The Delta I noise contributions of chip internal gates are generally considered negligible.
The factors which can make Delta I noise a design problem in the logic of modern high-performance computers are the parallelism of the data flow paths, the high speed drivers used and the great difficulty of providing adequate decoupling capacitors for the effective inductance of a dense multichip module. When one Delta I noise contributor switches, many other logically related contributors are likely to do so. If, for example, many drivers within a given chip or within neighboring chips can switch simultaneously, there is a data-dependent potential for generating Delta I noise. This noise may be sufficient either to delay the desired switchings or to impress excessive amounts of Delta I noise into quiescent drivers and their receivers. The latter condition can cause the reading and retention of spurious data.